1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, particularly to a floating gate type non-volatile semiconductor memory device.
2. Description of the Related Art
FIG. 1(a) is a plan view showing a constitution of a conventional non-volatile semiconductor memory device, FIG. 1(b)is an enlarged section view taken along the line X--X in FIG. 1(a), and FIG. 1(c) is an enlarged section view taken along the line Y--Y in FIG. 1(a), respectively.
As a non-volatile semiconductor memory device which is capable of writing and erasing data, an Electrically Erasable Programmable ROM (FLASH MEMORY) (hereinafter, referred to as an EPROM) has been heretofore known, which is a field effect transistor wherein a first gate insulating film is arranged on a channel region formed between source and drain regions on a surface of a semiconductor substrate, and a control gate capacitively coupled to a floating gate via a second gate insulating film is formed thereon.
This conventional semiconductor memory device stores the difference between threshold voltages in accordance with the difference between charge storage states in the floating gate in the form of "0" and "1" of data.
As shown in FIGS. 1(a), 1(b), and 1(c), source and drain regions 1 and 2 are formed on a surface of a P-type semiconductor substrate 7, and a first insulating film 8, a floating gate 51, a second insulating film 9, and a control gate 5 are sequentially formed on a channel region formed between the source and drain regions 1 and 2. An element is electrically isolated from other adjacent elements by the second insulating film 9 serving as a field oxide film. A polycrystalline silicon to which phosphorus is introduced is ordinarily used as the floating gate 51. In this embodiment, cells adjacent to each other in the vertical direction share the source and drain regions 1 and 2, as shown in FIG. 1(a), and they use the source and drain regions 1 and 2 also as wirings. The source and drain regions 1 and 2 are separated from the floating-gate 51 by a fourth insulating film 13.
In order to increase an integration density in such floating gate type non-volatile semiconductor memory device, reductions in a gate length of the floating gate and an interval between memory cells have been intended. Furthermore, to achieve this object, an exposing to form the floating gate has been carried out using a reduction projection exposing apparatus.
Even when the exposing is carried out by the above mentioned reduction projection exposing apparatus, however, since there is a limitation to the reduction of the gate length of the floating gate and the interval between the memory cells because of the inherent limitation due to a resolution of the reduction exposing projection apparatus, there is a limitation to the increase in the integration density of the floating gate type non-volatile semiconductor memory device. Therefore, there is a minimum dimension determined by the limitation to the resolution of such reduction exposing projection apparatus.
The memory cell, adjacent to another memory cell along the direction perpendicular to the axis connecting the source and drain regions, is separated from the other memory cells by a distance determined the minimum dimension described. To express two states "0" and "1" of data, the width of the memory cell and the width of the separation region between the memory cells are necessary and each memory cells and separation region must be more than the minimum dimension. For this reason, the memory structure expressing two data states "0" and "1", covers a width twice the minimum dimension, when viewed along the line perpendicular to the axis connecting the source and drain regions.